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NCMOS NMini Mold Package NHighly Accurate : 2% (50ms ~ 200ms) (80ms ~ 400ms) NLow Power Consumption : 1.0A (VIN = 2.0V) NBuilt-In Delay Circuit (1ms ~ 50ms)
GMicroprocessor reset circuitry GMemory battery back-up circuits GPower-on reset circuits GPower failure detection GSystem battery life and charge voltage monitors GDelay circuitry
2
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-channel open drain output configurations are available. Since the delay circuit is built-in, peripherals are unecessary and high density mounting is possible.
Highly Accurate : Detect voltage 2% Low Power Consumption : TYP 1.0 A [ VIN=2.0V ] Detect Voltage Range : 1.6V ~ 6.0V in 0.1V increments Operating Voltage Range : 0.7V ~ 10.0V Detect Voltage Temperature Characteristics : TYP 100ppm/C Built-In Delay Circuit : 1ms ~ 50ms, 50ms ~ 200ms, 80ms ~ 400ms Output Configuration : N-channel open drain or CMOS Ultra Small Packages : SOT-23 (150mW) mini-mold : SOT-89 (500mW) mini-power mold : TO-92 (300mW) * No parts are available with an accuracy of 1%
157
2
PIN NUMBER SOT-23 3 2 1 2 3 1 2 3 1 1 2 3
PIN V IN VSS VOUT
SOT-89 TO-92 (T) TO-92 (L) NAME
FUNCTION Supply Voltage Input Ground Output
158
GOrdering Information
XC61F XXXXXXX
DESIGNATOR a
b
c
d
DESCRIPTION Output Configuration : C = CMOS N = N-ch open drain Detect Voltage (VDF) : 25 = 2.5V 38 = 3.8V Output Delay : 1 = 50ms to 200ms 4 = 80ms to 400ms 5 = 1ms to 50ms Detect Accuracy : 2 = within 2.0%
DESIGNATOR e
DESCRIPTION Package Type : M = SOT-23 P = SOT-89 T = TO-92 (Regular) L = TO-92 (Custom pin Configuration) Device Orientation : R = Embossed Tape ( Right ) L = Embossed Tape ( Left ) H: Paper Tape (TO-92) B: Bag (TO-92)
2
f
GSOT-23
159
GSOT-89
2
GTO-92
160
GSOT-23, SOT-89
qwer
w q
r e
2
q Represents the integer of the Detect Voltage and the Output Configuration CMOS output (XC61FC series) DESIGNATOR CONFIGURATION CMOS A CMOS B CMOS C CMOS D CMOS E CMOS F CMOS H VOLTAGE (V) 0.w 1.w 2.w 3.w 4.w 5.w 6.w N-channel open drain (XC61FN series) DESIGNATOR CONFIGURATION VOLTAGE (V) N-ch K 0.w N-ch L 1.w N-ch M 2.w N-ch N 3.w N-ch P 4.w N-ch 5.w R 6.w N-ch S e Indicates the presence of delay time DESIGNATOR 5 6 7 DELAY TIME 50 to 200ms 80 to 400ms 1 to 50ms
w Represents the decimal number of the Detect Voltage DESIGNATOR VOLTAGE (V) DESIGNATOR VOLTAGE (V) q.5 q.0 5 0 q.6 q.1 6 1 q.7 q.2 7 2 q.3 q.8 8 3 q.9 q.4 9 4
r Represents the assembly lot no. Based on internal standards
GTO-92
q
1 2345 67 1
w
w w w e
2345 67
r
t y
2%
u
161
PARAMETER Input Voltage Output Current Output Voltage
CMOS N-ch open drain SOT-23 Continuous Total Power Dissipation SOT-89 TO-92
SYMBOL VIN IOUT VOUT
RATINGS 12 50 VSS -0.3 VIN +0.3 9 150 VSS -0.3 500 300 -30 -40 +80 +125
UNITS V mA V
Pd
mW C C
2
Operating Ambient Temperature Storage Temperature
Topr Tstg
O
O
PARAMETER Detect Voltage Hysteresis Range
SYMBOL V DF VHYS
CONDITIONS
MIN VDF (T)
x 0.98
TYP VDF (T) VDF
x 0.05
MAX VDF (T)
x 1.02
UNITS V V
CIRCUIT 1 1
VDF
x 0.02
VDF
x 0.08
Supply Current
ISS
Operating Voltage
V IN N-ch
Output Current
IOUT P-ch
VIN=1.5V =2.0V =3.0V =4.0V =5.0V VDF=1.6V to 6.0V VDS=0.5V VIN=1.0V =2.0V =3.0V =4.0V =5.0V VDS=2.1V VIN=8.0V ( CMOS output )
0.9 1.0 1.3 1.6 2.0 0.7 2.2 7.7 10.1 11.5 13.0 -10.0 100
2.6 3.0 3.4 3.8 4.2 10.0
A
2
V
1
3 mA
4 ppm/C 200 ms 5
Detect Voltage Temperature Characteristics Transient Delay Time (VDR VOUT inversion)
VDF Topr * VDF tDLY * VIN changes from 0.6V to 10V 50
162
GFunctional Description ( CMOS output )
q When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN , output (VOUT) will be equal to the input at VIN. Note that high impedeance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage. w When VIN falls below VDF , VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-channel open drain configurations. e When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage. r When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level. t Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. y Following transient delay time, VIN will be output at VOUT. Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up. Notes : 1. 2. The difference between VDR and VDF represents the hysteresis range. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the VDR level.
2
GTiming Chart
Input Voltage (VIN)
y
Detect Release Voltage (VDR) Detect Voltage (VDF)
Minimum Operating Voltage(VMIN) Ground Voltage (VSS)
Output Voltage (VOUT)
Propagation Delay Time (tDLY)
Ground Voltage (VSS)
q
w
e
r
t
y
163
GNotes on Use
1. 2. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added. ( refer to N.B. 1 - (1) below ) When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT ) does not exist. ( refer to N.B. 1 - (2) below ) With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. If a resistor (RIN ) must be used, then please use with as small a level of input impedance as possible in order to control the occurences of oscillation as described above. Further, please ensure that RIN is less than 10k
IN
3.
2
4. 5.
GN.B.
1. Oscillation (1) Oscillation as a result of output current with the CMOS output configuration : When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow through RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current : Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates ( during release and detect operations ). Consequently, oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this through current ( Diagram 3 ). Since hysteresis exists during detect operations, oscillation is unlikely to occur.
164
2
165
(1) SUPPLY CURRENT vs. INPUT VOLTAGE
2
(2) DETECT VOLTAGE, RELEASE VOLTAGE vs. AMBIENT TEMPERATURE
(3) OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS
166
(4) N-CHANNEL DRIVER OUTPUT CURRENT vs. VDS
2
(5) N-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
(6) P-CHANNEL DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
(7) AMBIENT TEMPERATURE vs. TRANSIENT DELAY TIME
167
(8) INPUT vs. TRANSIENT DELAY TIME
2
168

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